Wiring board and method of fabricating the same

ABSTRACT

A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of a Japanese Patent Application No.2008-259016 filed on Oct. 3, 2008, in the Japanese Patent Office, thedisclosure of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a wiring board having electrode pads,conductor patterns connected to the electrode pads and an insulatorlayer embedded with the electrodes and the conductor patterns, and to amethod of fabricating such a wiring board.

2. Description of the Related Art

Wiring boards having various shapes and structures have been proposedfor use in mounting thereon electronic components such as semiconductorchips. Recently, there are increased demands to reduce the thickness andsize of the wiring board mounted with the semiconductor chip, due to thereduced thickness and size of the semiconductor chip.

Known methods of forming thin wiring boards include the so-calledbuild-up method, for example. The build-up method fabricates amulti-level (or multi-layer) wiring board by stacking on a coresubstrate build-up layers made of an epoxy resin material, for example,in order to form interlayer insulators for the wirings.

The core substrate is made of a prepeg material or the like, andsupports the soft build-up layer prior to curing and suppresses warpingcaused by the curing of the build-up layer, during the fabricationprocess of the wiring board. However, the thickness of the coresubstrate, which forms the base for the wiring board, interferes withthe further reduction in the thickness of the wiring board that isfabricated using the build-up method.

In order to further reduce the thickness of the wiring board that isfabricated using the build-up method, a method has been proposed toremove a support plate which supports the wiring board (or build-uplayer) after forming the wiring board on the support plate by thebuild-up method, in a Japanese Laid-Open Patent Publication No.2005-5742, for example.

FIG. 1 is a cross sectional view illustrating an example of aconventional wiring board. As illustrated in FIG. 1, an electrode pad 1is formed on a support plate (not shown) which is removed by etching,for example, and an insulator layer 2 made of a resin material is formedto cover the periphery of the electrode pad 1. The electrode pad 1 isconnected to a conductor pattern 3, such as a via plug. The electrodepad 1 may be formed by a stacked structure made up of an Au layer 1A anda Ni layer 1B, for example.

When forming the wiring board on the support plate using the build-upmethod, a surface 2A of the insulator layer 2 and a surface 1C of theelectrode pad 1 are formed on the same plane. For this reason,delamination occurs at a boundary surface between a side surface of theelectrode pad 1 and the insulator layer 2, at a portion indicated by Ain FIG. 1.

As a countermeasure against the delamination described above, astructure has been proposed to form a wall portion that extends from anexposed surface of the electrode pad towards an opposite side from theexposed surface by modifying the shape of the electrode pad, in aJapanese Laid-Open Patent Publication No. 2005-244108, for example.However, when the shape of the electrode pad is complex as in the caseof this proposed electrode pad structure, the number of processesrequired to form the electrode pad increases, to thereby increase thefabrication cost of the wiring board.

On the other hand, a structure in which the electrode pad is embedded inthe insulator layer has been proposed in a Japanese Laid-Open PatentPublications No. 2004-64082 and No. 2003-229512, for example. However,according to this proposed structure, the delamination at the boundarysurface between the electrode pad and the insulator layer cannot besuppressed satisfactorily, and it is difficult to prevent thereliability of the wiring board from deteriorating due to thedelamination.

SUMMARY OF THE INVENTION

Accordingly, it is a general object of the present invention to providea novel and useful wiring board and method of fabricating the same, inwhich the problems described above are suppressed.

Another and more specific object of the present invention is to providea wiring board and a method of fabricating the same, which suppressesdelamination from being generated between a side surface of an electrodepad and a side surface of an insulator layer, to thereby improve thereliability of the wiring board.

According to one aspect of the present invention, there is provided awiring board comprising an electrode pad having a first surface and asecond surface located on an opposite side from the first surface; aconductor pattern connected to the first surface of the electrode pad;and an insulator layer embedded with the electrode pad and the conductorpattern, wherein the insulator layer covers an outer peripheral portionof the second surface of the electrode pad.

According to one aspect of the present invention, there is provided amethod of fabricating a wiring board, comprising an electrode padforming step forming an electrode pad on a support plate made of a firstmetal; a projecting part forming step forming, on the support plate at aportion opposing the electrode pad, a projecting part which exposes asurface of the electrode pad on a side opposing the support plate andcontacts the electrode pad, by etching the support plate; an insulatorlayer forming step forming an insulator layer covering the electrodepad, the projecting part, and a surface of the support plate formed withthe projecting part; a conductor pattern forming step forming, on theinsulator layer, a conductor pattern connected to the electrode pad; anda support plate removing step removing the support plate formed with theprojecting part by an etching, after the conductor pattern forming step,to thereby expose a portion of the surface of the electrode pad on theside opposing the support plate and form in the insulator layer anopening having a shape corresponding to a shape of the projecting part.

According to one aspect of the present invention, there is provided amethod of fabricating a wiring board, comprising a metal layer formingstep forming a metal layer on a support plate made of a first metal; anelectrode pad forming step forming an electrode pad on the metal layer;a projecting part forming step forming a projecting part by etching themetal layer, and exposing an outer peripheral portion of a surface ofthe electrode pad in contact with the projecting part; an insulatorlayer forming step forming an insulator layer to cover the projectingpart, the electrode pad, and a surface of the support plate formed withthe projecting part, after the projecting part forming step; a conductorpattern forming step forming, on the insulator layer, a conductorpattern connected to the electrode pad; a support plate removing stepremoving the support plate by an etching, after the conductor patternforming step; and a projecting part removing step removing theprojecting part, after the conductor pattern forming step, to therebyexpose a portion of the surface of the electrode pad in contact with theprojecting part and form in the insulator layer an opening having ashape corresponding to a shape of the projecting part.

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view illustrating an example of aconventional wiring board;

FIG. 2 is a cross sectional view illustrating a semiconductor device ina first embodiment of the present invention;

FIGS. 3 through 12 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the first embodiment of thepresent invention;

FIGS. 13 through 16 are cross sectional views for explaining otherfabrication processes of the semiconductor device in the firstembodiment of the present invention;

FIG. 17 is a cross sectional view illustrating the semiconductor devicein a modification of the first embodiment of the present invention;

FIG. 18 is a cross sectional view illustrating the semiconductor devicein a second embodiment of the present invention;

FIGS. 19 through 25 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the second embodiment of thepresent invention;

FIGS. 26 through 31 are cross sectional views for explaining otherfabrication processes of the semiconductor device in the secondembodiment of the present invention;

FIGS. 32 through 39 are cross sectional views for explaining still otherfabrication processes of the semiconductor device in the secondembodiment of the present invention;

FIG. 40 is a cross sectional view illustrating the semiconductor devicein a third embodiment of the present invention;

FIGS. 41 through 49 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the third embodiment of thepresent invention;

FIG. 50 is a cross sectional view illustrating the semiconductor devicein a fourth embodiment of the present invention;

FIGS. 51 through 59 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the fourth embodiment of thepresent invention;

FIG. 60 is a cross sectional view illustrating an example of anotherwiring board;

FIG. 61 is a cross sectional view illustrating the semiconductor devicein a modification of the second embodiment of the present invention;

FIG. 62 is a cross sectional view illustrating the semiconductor devicein a modification of the third embodiment of the present invention; and

FIG. 63 is a cross sectional view illustrating the semiconductor devicein a modification of the fourth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will be given of each embodiment of the present invention,by referring to FIGS. 2 through 63.

First Embodiment

FIG. 2 is a cross sectional view illustrating a semiconductor device ina first embodiment of the present invention. The semiconductor deviceaccording to the present invention is also referred to as asemiconductor package.

A semiconductor device 10 of this first embodiment includes a wiringboard 11 and an electronic component 13. The wiring board 11 includesstacked insulator layers 21, 22 and 23, electrode pads 25, conductorpatterns 27 and 28, vias 31, pads 32 for external connection, and asolder resist layer 34.

The insulator layer 21 is stacked on a surface 22A of the insulatorlayer 22. The electrode pads 25 and via parts 44 are embedded in theinsulator layer 21, and the via part 44 forms a constituent element ofthe conductor pattern 27. The insulator layer 21 includes openings 37and 38. The opening 37 is provided in a portion of the insulator layer21 on the opposite side from a portion of the insulator layer 21 makingcontact with the surface 22A of the insulator layer 22. The opening 37exposes a portion of a surface 41A of a metal layer 41, where a terminal12 for external connection and electrically connecting to the electroniccomponent 13 is provided. The metal layer 41 forms the electrode pad 25,and the surface 41A forms a second surface of the electrode pad 25. Afirst surface of the electrode pad 25 will be described later. Theterminal 12, which electrically connects the wiring board 11 to theelectronic component 13, is provided in the opening 37 by solder or Aubump, for example. The insulator layer 21 is provided to cover an outerperipheral portion of the surface 41A of the metal layer 41.

By covering the outer peripheral portion of the surface of the electrodepad 25 located on the side where the terminal 12 is provided, that is,by covering the outer peripheral portion of the surface 41A of the metallayer 41, it is possible to suppress delamination from being generatedbetween the side surface of the electrode pad 25 and the side surface ofthe insulator layer 21. As a result, the reliability of the wiring board11 can be improved.

For example, the width of the outer peripheral portion of the surface41A of the metal layer 41 covered by the insulator layer 21 maypreferably be 0.1 μm to 6 μm, and more preferably be 1 μm to 3 μm.

The opening 37 has a shape that widens from the electrode pad 25 towardsthe electronic component 13. Because the shape of the opening 37 widensfrom the electrode pad 25 towards the electronic component 13, that is,towards the surface 21A of the insulator layer 21, it is possible toeasily provide the terminal 12 within the opening 37.

In a case where the metal layer 41 has a diameter of 100 μm, thediameter of the opening 37 at the portion connecting to the metal layer41 can be 80 μm to 90 μm. For example, the depth of the opening 37 maypreferably be 1 μm to 30 μm, and more preferably be 20 μm.

The opening 38 is provided in the insulator layer 21 at a portion makingcontact with the insulator layer 22. The opening 38 exposes a surface42A of a metal layer 42 forming the electrode pad 25. The surface 42A ofthe metal layer 42 forms the first surface of the electrode pad 25.

The insulator layer 22 is provided between the insulator layer 21 andthe insulator layer 23. The insulator layer 22 contacts a surface 21B ofthe insulator layer 21 and a surface 23A of the insulator layer 23. Awiring part 45 forming the conductor pattern 27 and a via part 48forming the conductor pattern 28 are embedded in the insulator layer 22.The insulator layer 22 has openings 47 that expose portions of thewiring part 45.

The insulator layer 23 is provided on a surface 22B of the insulatorlayer 22. A wiring part 49 and the vias 31 are embedded in the insulatorlayer 23. The insulator layer 23 has openings 52 exposing portions ofthe wiring part 49.

For example, the insulator layers 21, 22 and 23 may be made of a resinmaterial. For example, the resin material includes epoxy resins,polyimide resins and the like. The insulator layers 21, 22 and 23 may bemade of the same material or, at least two of the insulator layers 21,22 and 23 may be made of mutually different materials.

The electrode pad 25 has a stacked structure formed by the first metallayer 41 connected to the terminal 12, and the second metal layer 42connected to the conductor pattern 27. For example, the metal layer 41may be formed by a Au layer having a thickness of 0.005 μm or greaterand preferably a thickness of 0.04 μm. For example, the metal layer 42may be formed by a Ni layer having a thickness of 1 μm to 10 μm, andpreferably a thickness of 5 μm. When the metal layer 41 is formed by theAu layer and the metal layer 42 is formed by the Ni layer, a Pd layer(not shown) having a thickness of 0.005 μm or greater, for example, maybe provided between the metal layers 41 and 42. When using the electrodepads 25 to mount the electronic component 13 on the wiring board 11, theelectrode pads 25 may have a diameter of 50 μm to 150 μm, for example.

The conductor pattern 27 includes the via parts 44, and the wiring part45 which is integrally formed on the via parts 44. The via part 44 isprovided in the opening 38. The via part 44 is connected to the metallayer 42. The wiring part 45 is provided on the surface 21B of theinsulator layer 21. For example, Cu may be used as a metal materialforming the conductor pattern 27.

The conductor pattern 28 includes the via parts 48, and the wiring part49 which is integrally formed on the via parts 48. The via part 48 isprovided in the opening 47. The via part 48 is connected to the wiringpart 45. The wiring part 49 is provided on the surface 22B of theinsulator layer 22. For example, Cu may be used as a metal materialforming the conductor pattern 28.

The via 31 is provided in the opening 52. The via 31 is connected to thewiring part 49. The vias 31 are integrally formed on the pads 32.

The pad 32 is provided on the surface 23B of the insulator layer 23, andis connected to the via 31. The pad 32 has a connection surface 32A. Forexample, the pad 32 is electrically connected to a circuit board (notshown) such as a mother board. When using the pad 32 s to makeelectrical connection to the circuit board, the pads 32 may have adiameter of 200 μm to 1000 μm, for example.

For example, Cu may be used as a material forming the via 31 and the pad32.

The solder resist layer 34 is provided on the surface 23B of theinsulator layer 23. The solder resist layer 34 has openings 34A thatexpose the connection surface 32A of the pad 32.

The electronic component 13 is mounted on the wiring board 11 via theterminals 12 and the electrode pads 25. For example, the electroniccomponent 13 may be formed by a semiconductor chip.

According to the wiring board of this first embodiment, the insulatorlayer 21 covers the outer peripheral portion of the surface of theelectrode pad 24 on the side where the terminal 12 is provided, that is,the surface 41A of the metal layer 41. Hence, it is possible to suppressthe generation of delamination between the side surface of the electrodepad 25 and the side surface of the insulator layer 21, and thereliability of the wiring board 11 can be improved.

In addition, according to the semiconductor device of this firstembodiment, the reliability of the electrical connection between thewiring board 11 and the electronic component 13 can be improved due tothe provision of the wiring board 11 having the structure describedabove.

FIGS. 3 through 12 are cross sectional views for explaining fabricationprocesses of the semiconductor device in this first embodiment of thepresent invention. In FIGS. 3 through 12, those parts that are the sameas those corresponding parts of the semiconductor device 10 illustratedin FIG. 2 are designated by the same reference numerals.

A description will now be given of the method of fabricating thesemiconductor device 10 of this first embodiment, by referring to FIGS.3 through 12. First, in a fabrication process or step (hereinaftersimply referred to as a process) illustrated in FIG. 3, a resist layer56 having openings 56A is formed on a surface 55A of a support plate 55that is made of a first metal. The opening 56A is formed to expose thesurface 55A of the support plate 55 in a portion corresponding to aregion where the electrode pad 25 is formed. For example, the supportplate 55 may be formed by a metal foil, a metal plate or the like. Thefirst metal may be Cu, for example. When Cu is used for the first metal,the thickness of the support plate 55 may be 35 μm to 250 μm, forexample.

Next, in an electrode pad forming process illustrated in FIG. 4, thefirst metal layer 41 and the second metal layer 42 are successivelystacked on the surface 55A of the support plate 55 exposed at theopenings 56A, by electroplating using the support plate 55 as a feedlayer, to thereby form the electrode pads 25. The metal layer 41 isformed by a first metal layer forming process, and the metal layer 42 isformed by a second metal layer forming process.

For example, the metal layer 41 may be formed by a Au layer having athickness of 0.005 μm or greater. When the Au layer is used for themetal layer 41, the metal layer 42 may be formed by a Ni layer having athickness of 1 μm to 10 μm, for example.

When mounting the electronic component 13 on the wiring board 11 usingthe electrode pads 25, the electrode pads 25 may have a diameter of 50μm to 150 μm, for example. When the metal layer 41 is formed by the Aulayer and the metal layer 42 is formed by the Ni layer, a Pd layer (notshown) having a thickness of 0.005 μm or greater, and preferably 0.02μm, for example, may be formed between the metal layers 41 and 42 byelectroplating.

In a process illustrated in FIG. 5, the resist layer 56 in FIG. 4 isremoved. Then, in a projecting part forming process illustrated in FIG.6, a portion of the support plate 55 in FIG. 5 located on the sideformed with the electrode pads 25 is etched, so as to etch the surface55A of the support plate 55 and form projecting parts 58 which makecontact with the surface 41A of the metal layer and exposes the outerperipheral portion of the surface 41A of the metal layer. Moreparticularly, the support plate 55 which is made of the first metal isselectively etched using an etchant which does not etch the metal layers41 and 42.

By carrying out an isotropic wet etching using the electrode pads 25 asa mask, it is possible to expose the outer peripheral portion of thesurface 41A of the metal layer 41 from the projecting parts 58,utilizing the side etching and undercut with respect to the supportplate 55 achieved by the etchant. In addition, it is possible to preventthe electrode pads 25 from being etched, by selectively etching thesupport plate 55.

The projecting part 58 has a shape which widens from the electrode pad25 towards the support plate 55. For example, the projecting part 58 mayhave a truncated cone shape. In this case, in the cross sectional view,the side surface of the projecting part 58 having the truncated coneshape may be curved inwards in a gull-wing shape relative to a centeraxis of the truncated cone shape. The shape of the projecting part 58 isapproximately the same as the shape of the opening 37 described above inconjunction with FIG. 2.

In a case where the diameter of the metal layer 41 is 100 μm, thediameter of the projecting part 58 at a portion contacting the metallayer 41 may be 80 μm to 90 μm, for example. In this case, the height ofthe projecting part 58 in a direction in which the layers are stackedmay be 1 μm to 30 μm.

Next, in an insulator layer forming process illustrated in FIG. 7, theinsulator layer 21 having the openings 38 is formed so as to cover theelectrode pads 25, the projecting parts 58, and the surface 55A of thesupport plate 55. The insulator layer 21 may be formed by stacking aresin film made of an epoxy resin, a polyimide resin or the like or, bycoating a resin.

As a result, the outer peripheral portion of the surface of theelectrode pad 25 located on the side where the terminal 12 is provided,that is, the surface 41A of the metal layer 41, is covered by theinsulator layer 21. For this reason, it is possible to suppressdelamination from being generated between the side surface of theelectrode pad 25 and the side surface of the insulator layer 21, and thereliability of the wiring board 11 can be improved.

The width of the outer peripheral portion of the surface 41A of themetal layer 41 covered by the insulator layer 21 may be 0.1 μm to 6 μm,and preferably 1 μm to 3 μm, for example.

The opening 38 is formed in a portion of the insulator layer 21 opposingthe surface 42A of the metal layer 42, to expose the surface 42A of themetal layer 42. For example, the opening 38 may be formed by laser beammachining. The thickness of the portion of the insulator layer 21provided on the surface 55A of the support plate 55 may be 55 μm to 60μm, for example.

Next, in a conductor pattern forming process illustrated in FIG. 8, theconductor pattern 27 is formed in the openings 38 and on the surface 21Bof the insulator layer 21 by a semiadditive method. Hence, the via part44 formed in the opening 38 is connected to the second metal layer 42.The via part 44 penetrates the portion of the insulator layer 21opposing the electrode pad 25 on the side where the projecting part 58is not formed. For example, Cu may be used as a material forming theconductor pattern 27.

Next, in a process illustrated in FIG. 9, processes similar to theprocesses described above in conjunction with FIGS. 7 and 8 arerepeated, in order to form the insulator layers 22 and 23, the conductorpattern 28, the vias 31, and the pads 32. For example, each of theinsulator layers 22 and 23 may be formed by a resin material. In thiscase, the resin material may be epoxy resins, polyimide resins or thelike, for example. When the insulator layers 22 and 23 are made of aresin, the thickness of each of the insulator layers 22 and 23 may be 25μm to 40 μm, for example. For example, Cu may be used for the conductorpattern 28, the vias 31, and the pads 32. In a case where the pad 32 hasa circular shape in a plan view, the diameter of the pad 32 may be 200μm to 1000 μm, for example.

Next, in a process illustrated in FIG. 10, the solder resist layer 34having the openings 34A which expose the connection surface 32A of thepads 32 is formed on the surface 235 of the insulator layer 23 by aknown method. Hence, a structure corresponding to the wiring board 11 isformed on the support plate 55.

Next, in a support plate removing process illustrated in FIG. 11, thesupport plate 55 formed with the projecting parts 58 illustrated in FIG.10 is removed by etching. Consequently, the surface 41A of the metallayer 41 is exposed, and the openings 37 having the shapes correspondingto the shapes of the projecting parts 58 are formed. More particularly,the support plate 55 formed with the projecting parts 58 is removedusing an etchant which selectively etches the support plate 55 but doesnot etch the electrode pads 25. As a result, the wiring board 11 of thisfirst embodiment is fabricated. The depth of the opening 37 may be 1 μmto 30 μm, and preferably 20 μm, for example.

Next, in a process illustrated in FIG. 12, the electronic component 13is mounted on the wiring board 11 via the terminals 12 and the electrodepads 25 (or the metal layer 41). Thus, the semiconductor device 10 ofthis first embodiment, provided with the electronic component 13 and thewiring board 11, is fabricated.

According to the method fabricating the wiring board of this firstembodiment, the support plate 55 is etched to form, at the portion ofthe support plate 55 confronting the electrode pad 25, the projectingpart 58 which exposes the outer peripheral portion of the surface(surface 41A of the metal layer 41) of the electrode pad 25 on the sideconfronting the support plate. Thereafter, the insulator layer 21 isformed to cover the electrode pad 25, the projecting part 58, and thesurface 55A of the support plate 55 on the side formed with theelectrode pad 25. Hence, the insulator layer 21 is formed on the surface(surface 41A of the metal layer 41) of the electrode pad 25 on the sideopposing the support plate 55, and the generation of delaminationbetween the side surface of the electrode pad 25 and the side surface ofthe insulator layer 21 is suppressed, to thereby improve the reliabilityof the wiring board 11.

FIGS. 13 through 16 are cross sectional views for explaining otherfabrication processes of the semiconductor device in the firstembodiment of the present invention, that may be used to fabricate thesemiconductor device in the first embodiment. In FIGS. 13 through 16,those parts that are the same as those corresponding parts of thestructure illustrated in FIG. 4 and the semiconductor device 10 of thefirst embodiment illustrated in FIG. 2 are designated by the samereference numerals.

A description will be given of the other fabrication processes that maybe used to fabricate the semiconductor device 10 of this firstembodiment, by referring to FIGS. 13 through 16. First, a processsimilar to the process of the first embodiment described above inconjunction with FIG. 3 is carried out to form the structure illustratedin FIG. 3.

Next, in a height adjusting layer forming process illustrated in FIG.13, a height adjusting layer 61 made of the first metal (metal formingthe support plate 55) is formed on the surface 55A of the support plate55 at portions corresponding to regions where the electrode pads 25 areformed, prior to forming the electrode pads 25. The height adjustinglayer 61 may be formed by electroplating using the support plate 55 as afeed layer. For example, Cu may be used for the first metal. When Cu isused for the first metal, the Cu layer forming the height adjustinglayer 61 may have a thickness of 5 μm to 15 μm, for example.

Next, in a process illustrated in FIG. 14, a process similar to theprocess described above in conjunction with FIG. 4 is carried out tosuccessively form the metal layer 41 and the metal layer 42 on a surface61A of the height adjusting layer 61.

Next, in a process illustrated in FIG. 15, the resist layer 56 in FIG.14 is removed. Then, in a projecting part forming process illustrated inFIG. 16, the portions of the support plate 55 located on the side wherethe electrode pads 25 are formed and the height adjusting layer 61 areetched, to etch the surface 55A of the support plate 55 and the sidewallof the height adjusting layer 61. As a result, projecting parts 62 whichcontact the surface 41A of the metal layer 41 and expose the outerperipheral portion of the surface 41A of the metal layer 41 are formed.The projecting part 62 is made up of a portion of the support plate 55and the height adjusting layer 61 that remains after the etching. Moreparticularly, in the projecting part forming process, an etchant whichselectively etches the support plate 55 and the height adjusting parts61 that are respectively made of the first metal, and does not etch themetal layers 41 and 42, is used to etch the support plate 55 and theheight adjusting layer 61.

Thereafter, processes similar to the processes described above inconjunction with FIGS. 7 through 12 are carried out, to fabricate thesemiconductor device 10 of this first embodiment.

According to the method of fabricating the semiconductor device of thisfirst embodiment utilizing the other fabrication processes, the heightadjusting layer 61 made of the first metal is formed on the supportplate 55 so that the height adjusting layer 61 will be interposedbetween the support plate 55 and the electrode pads 25 formedthereafter, and the electrode pads 25 are then formed on the heightadjusting layer 61. In addition, the portions of the support plate 55where the electrode pads 25 are formed and the height adjusting layer 61are etched, in order to reduce the amount of etching or the etching timerequired to form the projecting parts 62. Hence, compared to the casewhere no height adjusting layer 61 is formed, it is possible to reducethe fabrication cost of the wiring board 11.

FIG. 17 is a cross sectional view illustrating the semiconductor devicein a modification of the first embodiment of the present invention. InFIG. 17, those parts that are the same as those corresponding parts ofthe semiconductor device 10 of the first embodiment illustrated in FIG.2 are designated by the same reference numerals.

As illustrated in FIG. 17, a semiconductor device 65 in thismodification of the first embodiment is provided with a wiring board 66,in place of the wiring board 11 provided in the semiconductor device 10of the first embodiment. Otherwise, the structure of the semiconductordevice 65 is basically the same as that of the semiconductor device 10.

The wiring board 66 includes pads 32 for use in mounting the electroniccomponent 13 on the wiring board 66, and electrode pads 25 for use inmaking electrical connections to a circuit board (not shown) such as amother board. In this case, the diameter of the pad 32 may be 50 μm to150 μm, for example. Further, the diameter of the electrode pad 25 maybe 200 μm to 1000 μm, for example.

The wiring board 66 of this modification of the first embodiment canobtain effects similar to those obtainable by the wiring board 11 of thefirst embodiment. In addition, the wiring board 66 can be fabricated byprocesses similar to those used to fabricate the wiring board 11, andthe effects obtainable by the fabrication processes of the wiring board66 are similar to those obtainable by the fabrication processes of thewiring board 11.

The semiconductor devices 10 and 65 have the Land Grid Array (LGA)structure in which the pads themselves on the side connecting to thecircuit board (not shown) function as terminals for external connection.However, the semiconductor devices 10 and 65 may have the Ball GridArray (BGA) structure in which the pads connect to solder balls or, thePin Grid Array (PGA) structure in which the pads connect to pins.

Second Embodiment

FIG. 18 is a cross sectional view illustrating the semiconductor devicein a second embodiment of the present invention. In FIG. 18, those partsthat are the same as those corresponding parts of the semiconductordevice 10 of the first embodiment illustrated in FIG. 2 are designatedby the same reference numerals.

As illustrated in FIG. 18, a semiconductor device 70 in this secondembodiment is provided with a wiring board 71, in place of the wiringboard 11 provided in the semiconductor device 10 of the firstembodiment. Otherwise, the structure of the semiconductor device 70 isbasically the same as that of the semiconductor device 10.

The wiring board 71 is provided with electrode pads 73, in place of theelectrode pads 25 provided in the wiring board 11. Otherwise, thestructure of the wiring board 71 is basically the same as that of thewiring board 11.

The electrode pad 73 includes, in addition to the structure of theelectrode pad 25, a third metal layer 75 which covers the surface 42A ofthe second metal layer 42. Otherwise, the structure of the electrode pad73 is basically the same as that of the electrode pad 25.

A surface 75A of the metal layer 75, located on the side opposite to theside connecting to the metal layer 42, is exposed at the opening 38formed in the insulator layer 21. The metal layer 75 is connected to theconductor pattern 27, that is, the via part 44, provided in the opening38. Hence, the electrode pads 73 electrically connect the electroniccomponent 13 and the conductor pattern 27.

The metal layer 75 is made of the same metal as the conductor pattern27, that is, the first metal used in the first embodiment. Preferably,the metal layer 75 is made of a metal which is less easily oxidized thanthe metal forming the metal layer 42. In a case where Cu is used for themetal forming the conductor pattern 27, Cu, for example, may be used asthe metal material forming the metal layer 75. When Cu is used as themetal material forming the metal layer 75, the thickness of the metallayer 75 may be 10 μm to 20 μm, and preferably 15 μm, for example. Cu isless easily oxidized than Ni.

Accordingly, by providing on the surface 42A of the metal layer 42 themetal layer 75 which is less easily oxidized than the metal layer 42,and connecting the metal layer 75 and the via part 44 forming theconductor pattern 27, it is possible to improve the reliability of theelectrical connection between the electrode pads 73 and the conductorpattern 27.

In addition, in the case where the metal material forming the conductorpattern 27 is Cu, it is possible to improve the bonding between the viapart 44 and the metal layer 75 by using Cu for the metal materialforming the metal layer 75. As a result, it is possible to furtherimprove the reliability of the electrical connection between theelectrode pads 73 and the conductor pattern 27 in this case.

When the electrode pads 73 are used to mount the electronic component 13on the wiring board 71, the diameter of the electrode pad 73 may be 50μm to 150 μm, for example. In this case, the pads 32 connect to acircuit board (not shown) such as a mother board, and the diameter ofthe pad 32 may be 200 μm to 1000 μm, for example.

Moreover, when the electrode pads 73 are used to connect to the circuitboard (not shown) such as the mother board, the diameter of theelectrode pad 73 may be 200 μm to 1000 μm, for example. In this case,the electronic component 13 is mounted on the pads 32, and the diameterof the pad 32 may be 50 μm to 150 μm, for example.

According to the wiring board 71 of this second embodiment, the metallayer 75 less easily oxidized than the metal layer 42 is provided on thesurface 42A of the metal layer 42, and the metal layer 75 is connectedto the via part 44 forming the conductor pattern. Hence, it is possibleto improve the reliability of the electrical connection between theelectrode pads 73 and the conductor pattern 27.

In a case where the metal layer 41 is formed by a Au layer and the metallayer 42 is formed by a Ni layer, a Pd layer (not shown) may be providedbetween the metal layers 41 and 42. In this case, the thickness of thePd layer may be 0.005 μm or greater, and preferably 0.02 μm, forexample.

FIGS. 19 through 25 are cross sectional views for explaining fabricationprocesses of the semiconductor device in this second embodiment of thepresent invention. In FIGS. 19 through 25, those parts that are the sameas those corresponding parts of the semiconductor device 70 illustratedin FIG. 18 are designated by the same reference numerals.

A description will now be given of the method of fabricating thesemiconductor device 70 of this second embodiment, by referring to FIGS.19 through 25. First, a first metal layer forming process and a secondmetal layer forming process similar to the processes described above inconjunction with FIGS. 3 and 4 of the first embodiment are carried outto form the structure illustrated in FIG. 4.

Next, in a third metal layer forming process illustrated in FIG. 19, thethird metal layer 75 made of the first metal less easily oxidized thanthe metal layer 42 is formed on the surface 42A of the metal layer 42 byelectroplating using the support plate 55 made of the first metal as afeed layer.

The third metal layer forming process forms the metal layer 75 to have athickness greater than the thickness of the metal layer 75 illustratedin FIG. 18, so that the metal layer 75 will has a sufficient thicknessto cover the surface 42A of the metal layer 42 after a projecting partforming process which will be described later in conjunction with FIG.21. In other words, the metal layer 75 is formed to a thickness that isa sum of the thickness of the metal layer 75 illustrated in FIG. 18 andan amount or thickness of the metal layer 75 that will be etched duringthe projecting part forming process, by taking into account the amountof etching made in the projecting part forming process. In a case wherethe first metal is Cu, the metal layer 75 may have a thickness of 30 μmto 50 μm, for example.

By forming the metal layer 75 to have the thickness greater than that ofthe metal layer 75 illustrated in FIG. 18 by taking into account theamount of the metal layer 75 etched in the projecting part formingprocess, it becomes possible to positively connect the metal layer 75and the via part 44 of the conductor pattern 27. Consequently, thereliability of the electrical connection between the metal layer 75 andthe conductor pattern 27 can be improved.

In addition, by using Cu for the metal material forming the conductorpattern 27 and the metal layer 75, it is possible to further improve thereliability of the electrical connection between the metal layer 75 andthe conductor pattern 27.

Next, in a process illustrated in FIG. 20, the resist layer 56 in FIG.19 is removed. Then, in the projecting part forming process illustratedin FIG. 21, a process similar to the process of the first embodimentdescribed above in conjunction with FIG. 6 is carried out to etch aportion of the support plate 55 located on the side formed with theelectrode pads 73 in FIG. 20, and the surface 55A of the support plate55 is etched. Hence, the projecting part 58 which contacts the surface41A of the metal layer 41 and exposes the outer peripheral portion ofthe surface 41A of the metal layer 41 is formed. In this state, themetal layer 75 which is made of the first metal which forms the supportplate 55 is also etched. However, the thickness of the metal layer 75 isset in advance in the process described above in conjunction with FIG.19 by taking into account the amount of the metal layer 75 that will beetched in the projecting part forming process. For this reason, theetching of the metal layer 75 in the projecting part forming processwill not cause the surface 42A of the metal layer 42 to become exposed.

In addition, by reducing the thickness of the metal layer 75 by theetching carried out in the projecting part forming process, theelectrode pad 73 made up of the metal layers 41, 42 and 75 is formed.The process illustrated in FIG. 4 and FIGS. 19 through 21 correspond tothe electrode pad forming process.

When Cu is used for the metal material forming the metal layer 75, thethickness of the metal layer 75 after the projecting part formingprocess may be 10 μm to 20 μm, and preferably 15 μm, for example.

Next, in an insulator layer forming process illustrated in FIG. 22, theinsulator layer 21 having the openings 38 is formed to cover theelectrode pads 73, the projecting parts 58, and the surface 55A of thesupport plate 55 located on the side formed with the projecting parts58.

Hence, the outer peripheral portion of the surface of the electrode pad73 on the side provided with the terminal 12, that is, the surface 41Aof the metal layer 41, is covered by the insulator layer 21. As aresult, it is possible to suppress the generation of delaminationbetween the side surface of the electrode pad 73 and the side surface ofthe insulator layer 21, and to improve the reliability of the wiringboard 71.

For example, the thickness of the insulator layer 21 provided on thesurface 55A of the support plate 55 may be 65 μm to 75 μm, for example.

Next, in a process illustrated in FIG. 23, processes similar to theprocesses of the first embodiment described above in conjunction withFIGS. 8 through 10, including the conductor pattern forming process, arecarried out, to form the conductor patterns 27 and 28, the vias 31, thepads 32, and the solder resist layer 34. Hence, a structurecorresponding to the wiring board 71 is formed on the support plate 55.

Next, in a support plate removing process illustrated in FIG. 24, thesupport plate 55 formed with the projecting parts 58 is removed by aprocess similar to the process of the first embodiment described abovein conjunction with FIG. 11. Thus, the openings 37 which expose thesurface 41A of the metal layer 41 and have shapes corresponding to theshapes of the projecting parts 58 are formed in the insulator layer 21.As a result, the wiring board 71 of this second embodiment isfabricated.

Next, in a process illustrated in FIG. 25, the electronic component 13is mounted on the wiring board 71 via the terminals 12 and the electrodepads (or metal layer 41). Therefore, the semiconductor device 70 of thissecond embodiment, including the electronic component 13 and the wiringboard 71, is fabricated.

According to the method of fabricating the wiring board 71 of thissecond embodiment, the metal layer 41 made of a metal different from thefirst metal is formed on the support plate 55, and the metal layer 42made of a metal different from the first metal is formed on the metallayer 42, and the metal layer 75 is formed on the surface 42A of themetal layer 42. This metal layer 75 is made of the first metal which isless easily oxidized than the metal layer 42. In addition, this metallayer 75 has a sufficient thickness that will enable the metal layer 75to cover the surface 42A of the metal layer 42 after the projecting partforming process. Accordingly, it is possible to improve the reliabilityof the electrical connection between the electrode pads 73 and theconductor pattern 27, because the metal layer 75 which is a constituentelement of the electrode pad 73 can be connected to the conductorpattern 27.

FIGS. 26 through 31 are cross sectional views for explaining otherfabrication processes of the semiconductor device in this secondembodiment of the present invention, that may be used to fabricate thesemiconductor device in the second embodiment. In FIGS. 26 through 31,those parts that are the same as those corresponding parts of thesemiconductor device 70 of the second embodiment illustrated in FIG. 18are designated by the same reference numerals.

A description will be given of the other fabrication processes that maybe used to fabricate the semiconductor device 70 of this secondembodiment, by referring to FIGS. 26 through 31. First, processessimilar to the processes of the first embodiment described above inconjunction with FIGS. 3 and 4, including the first metal layer formingprocess and the second metal layer forming process, are carried out toform the structure illustrated in FIG. 4.

Next, in a process illustrated in FIG. 26, the third metal layer 75 madeof the first metal less easily oxidized than the metal layer 42 isformed on the surface 42A of the metal layer 42 by electroplating usingthe support plate 55 made of the first metal as a feed layer. Hence, theelectrode pads 73 made up of the metal layers 41, 42 and 75 are formedon the surface 55A of the support plate 55. The processes illustrated inFIGS. 4 and 26 correspond to the electrode pad forming process.

For example, Cu may be used for the first meal. When Cu is used for themetal material forming the metal layer 75, the thickness of the metallayer 75 may be 10 μm to 20 μm, and preferably 15 μm, for example.

Next, in a protection layer forming process illustrated in FIG. 27, aprotection layer 78 is formed on the surface 75A of the metal layer.This protection layer 78 prevents the metal layer 75 from being etchedwhen etching the support plate in a projecting part forming processwhich will be described later in conjunction with FIG. 29.

The protection layer 78 may be formed by electroplating using thesupport plate 55 as a feed layer. The protection layer 78 is made of ametal material different from the first metal. For example, a Sn layer,a Sn—Pb layer or the like, formed by electroplating, may be used for theprotection layer 78. In this case, the thickness of the protection layer78 may be 1 μm to 5 μm, for example.

Next in a process illustrated in FIG. 28, the resist layer 56 in FIG. 27is removed. Then, in the projecting part forming process illustrated inFIG. 29, the portions of the support plate 55 on the side formed withthe electrode pads 73 in FIG. 28 are etched, and the surface 55A of thesupport plate 55 is etched. As a result, the projecting part 58, whichcontacts the surface 41A of the metal layer 41 and exposes the outerperipheral portion of the surface 41A of the metal layer 41, is formed.More particularly, the support plate 55 is etched using an etchant thatselectively etches the support plate 55 made of the first metal but doesnot etch the metal layers 41 and 42 and the protection layer 78.

By carrying out an isotropic wet etching using the electrode pads 73 asa mask, it is possible to expose the outer peripheral portion of thesurface 41A of the metal layer 41 from the projecting parts 58,utilizing the side etching and undercut with respect to the supportplate 55 achieved by the etchant.

In addition, the protection layer 78 which is made of the metaldifferent from the first metal is formed on the surface 75A of the metallayer 75 which is made of the first metal forming the support plate 55,and the projecting parts 58 are formed on the support plate 55 byetching the support plate 55. For this reason, it is possible to preventthe metal layer 75 from being etched in the projecting part formingprocess.

Next, in a protection layer removing process illustrated in FIG. 30, theprotection layer 78 is removed using an etchant, such as afluorine-hydrogen-peroxide system etchant, which removes only theprotection layer 78 in FIG. 29. As a result, the surface 75A of themetal layer 75 is exposed.

Next, in an insulator layer forming process illustrated in FIG. 31, theinsulator layer 21 having the openings 38 is formed to cover theelectrode pads 73, the projecting parts 58, and the surface 55A of thesupport plate 55 on the side formed with the projecting parts 58.

Accordingly, the outer peripheral portion of the surface of theelectrode pad 73 on the side provided with the terminal 12, that is, thesurface 41A of the metal layer 41, is covered by the insulator layer 21.For this reason, it is possible to suppress the generation ofdelamination between the side surface of the electrode pad 73 and theside surface of the insulator layer 21, and to improve the reliabilityof the wiring board 71.

The thickness of the insulator layer 21 provided on the surface 55A ofthe support plate 55 may be 65 μm to 75 μm, for example.

The semiconductor device 70 of this second embodiment is fabricated bycarrying out processes similar to the processes described above inconjunction with FIGS. 23 through 25, after the insulator layer formingprocess.

According to the method of fabricating the semiconductor device of thissecond embodiment utilizing the other fabrication processes, theprotection layer 78 made of the metal different from the first metal isformed on the surface 75A of the metal layer made of the first metalforming the support plate 55. Thereafter, the projecting parts 58 areformed on the support plate 55 by etching the support plate 55. Hence,it is possible to prevent the metal layer 75 from being etched in theprojecting part forming process.

According to the method of fabricating the semiconductor device of thissecond embodiment utilizing the other fabrication processes, it ispossible to obtain effects similar to those obtainable by thefabrication processes described above in conjunction with FIGS. 19through 25.

FIGS. 32 through 39 are cross sectional views for explaining still otherfabrication processes of the semiconductor device in the secondembodiment of the present invention, that may be used to fabricate thesemiconductor device in the second embodiment. In FIGS. 32 through 39,those parts that are the same as those corresponding parts of thesemiconductor device 70 of the second embodiment illustrated in FIG. 18are designated by the same reference numerals.

A description will be given of this still other fabrication processesthat may be used to fabricate the semiconductor device 70 of this secondembodiment, by referring to FIGS. 32 through 39. First, a processsimilar to the process of the first embodiment described above inconjunction with FIG. 3 is carried out to form the structure illustratedin FIG. 3.

Next, in a metal layer forming process for forming the projecting partillustrated in FIG. 32, a metal layer 81 for forming the projecting partis formed on the surface 55A of the support plate 55 at portions exposedby the openings 56A. More particularly, the metal layer 81 is formed byelectroplating using the support plate 55 as a feed layer. For example,a Sn layer, a Sn—Pb layer or the like, formed by electroplating, forexample, may be used for the metal layer 81. In this case, the height ofthe metal layer 81 may be 1 μm to 30 μm, and preferably 20 μm, forexample.

Next, in an electrode pad forming process illustrated in FIG. 33, theelectrode pads 73 are formed by successively stacking the metal layer41, the metal layer 42 and the metal layer 75 by processes similar tothe process described above in conjunction with FIGS. 4 and 26.

Next, in a process illustrated in FIG. 34, the resist layer 56 in FIG.33 is removed. Then, in a projecting part forming process illustrated inFIG. 35, the metal layer 81 is etched to form projecting parts 81-1which expose the outer peripheral portion of the surface 41A of themetal layer 41 formed on the side making contact with the metal layer81. More particularly, the projecting parts 81-1 are formed by using anetchant, such as a fluorine-hydrogen-peroxide system etchant, whichremoves only the metal layer 81.

By carrying out an isotropic wet etching using the electrode pads 73 asa mask, it is possible to expose the outer peripheral portion of thesurface 41A of the metal layer 41 from the projecting parts 81-1,utilizing the side etching and undercut with respect to the metal layer81 achieved by the etchant.

For example, the projecting part 81-1 may have a truncated cone shape.In this case, in the cross sectional view, the side surface of theprojecting part 81-1 having the truncated cone shape may be curvedinwards in a gull-wing shape relative to a center axis of the truncatedcone shape.

It is possible to prevent the electrode pads 73 from being etched by useof an etchant which etches only the metal layer 81.

In a case where the diameter of the metal layer 41 is 100 μm, thediameter of the projecting part 81-1 at the portion in contact with themetal layer 41 may be 80 μm to 90 μm, for example.

Next, in an insulator layer forming process illustrated in FIG. 36, theinsulator layer 21 having the openings 38 is formed to cover the etchedprojecting parts 81-1, the electrode parts 73, and the surface 55A ofthe support plate 55 on the side formed with the projecting parts 81-1.

Next, in a process illustrated in FIG. 37, a process similar to theprocess described above in conjunction with FIG. 23, including theconductor pattern forming process, is carried out to form the conductorpatterns 27 and 28, the vias 31, the pads 32, and the solder resistlayer 34. As a result, a structure corresponding to the wiring board 71is formed on the support plate 55.

Next, in a support plate removing process illustrated in FIG. 38, aprocess similar to the process described above in conjunction with FIG.24 is carried out to remove the support plate 55. As a result, theprojecting parts 81-1 are exposed.

Then, in a projecting part removing process illustrated in FIG. 39, theprojecting parts 81-1 are removed to expose a portion of the surface(surface 41A of the metal layer 41) of the electrode pads 73 on the sidein contact with the projecting parts 81-1, and the openings 37 havingshapes corresponding to the shapes of the projecting parts 81-1 areformed in the insulator layer 21. As a result, the wiring board 71 isfabricated.

After the projecting part removing process, a process similar to theprocess described above in conjunction with FIG. 25 is carried out tofabricate the semiconductor device 70 of this second embodiment.

According to the method of fabricating the semiconductor device of thissecond embodiment utilizing the still other fabrication processes, themetal layer 81 is formed so that the metal layer 81 will be interposedbetween the support plate 55 and the electrode pads 73 formedthereafter. After the electrode pads 73 are formed by the electrode padforming process, the metal layer 81 is etched to form the projectingparts 81-1 which expose the outer peripheral portion of the surface 41Aof the metal layer 41. Thereafter, the insulator layer 21 is formed tocover the projecting parts 81-1, the electrode pads 73, and the surface55A of the support plate 55 on the side formed with the projecting parts81-1. For this reason, compared to the case where the openings 37 areformed by etching the support plate 55, it is possible to reduce theinconsistency in the depths of the openings 37 that are formed.

Furthermore, according to the method of fabricating the semiconductordevice of this second embodiment utilizing the still other fabricationprocesses, it is possible to obtain effects similar to those obtainableby the fabrication processes described above in conjunction with FIGS.19 through 25.

Third Embodiment

FIG. 40 is a cross sectional view illustrating the semiconductor devicein a third embodiment of the present invention. In FIG. 40, those partsthat are the same as those corresponding parts of the semiconductordevice 70 of the second embodiment illustrated in FIG. 18 are designatedby the same reference numerals.

As illustrated in FIG. 40, a semiconductor device 85 in this thirdembodiment is provided with a wiring board 86 in place of the wiringboard 71 of the semiconductor device 70 of the second embodiment.Otherwise, the structure of the semiconductor device 85 is basically thesame as that of the semiconductor device 70.

The wiring board 86 has electrode pads 88 in place of the electrode pads73 of the wiring board 71. Otherwise, the structure of the wiring board86 is basically the same as that of the wiring board 71.

In the electrode pad 88, the outer peripheral side surfaces of the(second) metal layer 42 are disposed on the inner side compared to theouter peripheral side surfaces of the (first and third) metal layers 41and 75. Otherwise, the electrode pad 88 is formed similarly to theelectrode pad 73.

Because the outer peripheral side surfaces of the metal layer 42 aredisposed on the inner side compared to the outer peripheral sidesurfaces of the metal layers 41 and 75, a recess 89 filled with theinsulator layer 21 is formed in the electrode pad 88. For this reason,the position of the electrode pad 88 is restricted by the insulatorlayer 21 within the recess 89, and the electrode pad 88 is morepositively embedded in the insulator layer 21.

Moreover, the contact area between the insulator layer 21 and theelectrode pad 88 increases by the provision of the recess 89, and it ispossible to improve the bonding between the insulator layer 21 and theelectrode pad 88.

For example, a distance B from the outer peripheral side surface of themetal layer 42 to the outer peripheral side surfaces of the metal layers41 and 75 may be 5 μm to 20 μm.

According to the wiring board 86 of this third embodiment, the outerperipheral side surfaces of the metal layer 42 are disposed on the innerside compared to the outer peripheral side surfaces of the metal layers41 and 75, and the recess 89 filled with the insulator layer 21 isformed in the electrode pad 88. For this reason, the position of theelectrode pad 88 is restricted by the insulator layer 21 within therecess 89, and the electrode pad 88 is more positively embedded in theinsulator layer 21. Moreover, because the contact area between theinsulator layer 21 and the electrode pad 88 increases by the provisionof the recess 89, it is possible to improve the bonding between theinsulator layer 21 and the electrode pad 88.

FIGS. 41 through 49 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the third embodiment of thepresent invention. In FIGS. 41 through 49, those parts that are the sameas those corresponding parts of the semiconductor device 85 of the thirdembodiment illustrated in FIG. 40 are designated by the same referencenumerals.

A description will be given of the method of fabricating thesemiconductor device 85 of this third embodiment, by referring to FIGS.41 through 49. First, a process similar to the process of the firstembodiment described above in conjunction with FIG. 3 is carried out toform the structure illustrated in FIG. 3.

Next, in a metal layer forming process for forming the projecting partillustrated in FIG. 41, a metal layer 91 for forming the projectingpart, made of the same metal as the metal layer 42, is formed on thesurface 55A of the support plate 55 at portions exposed by the openings56A. More particularly, the metal layer 91 is formed by electroplatingusing the support plate 55 as a feed layer. When the metal layer 42 isformed by a Ni layer, for example, the metal layer 91 may be formed by aNi layer. The thickness of the metal layer 91 may be 1 μm to 30 μm, andpreferably 20 μm, for example.

Next, in a process illustrated in FIG. 42, a process similar to theprocess of the second embodiment described above in conjunction withFIG. 33 is carried out to successively stack the metal layer 41, themetal layer 42 made of the same metal material as the metal layer 91,and the metal layer 75 on a surface 91A of the metal layer 91, to formthe electrode pads 88. At this stage, the recess 89 is not yet formed inthe electrode pad 88.

Next, in a process illustrated in FIG. 43, the resist layer 56 isremoved. Then, in a projecting part forming process illustrated in FIG.44, the metal layer 91 is etched using an etchant which etches only themetal layer 91 and does not etch the metal layer 41, the metal layer 75and the support plate 55. As a result, projecting parts 91-1 whichexpose the outer peripheral portion of the surface 41A of the metallayer 41 are formed.

By carrying out an isotropic wet etching using the electrode pads 88 asa mask, it is possible to expose the outer peripheral portion of thesurface 41A of the metal layer 41 from the projecting parts 91-1,utilizing the side etching and undercut with respect to the metal layer91 achieved by the etchant.

For example, the projecting part 91-1 may have a truncated cone shape.In this case, in the cross sectional view, the side surface of theprojecting part 91-1 having the truncated cone shape may be curvedinwards in a gull-wing shape relative to a center axis of the truncatedcone shape.

In the projecting part forming process, the recesses 89 are formedbecause the sidewalls of the metal layer 42, which is made of the samemetal material as the metal layer 91, are also etched. Hence, theelectrode pads 88 having the recesses 89 are formed by an electrode padforming process.

Accordingly, it is possible to simultaneously form the recesses 89 andthe projecting parts 91-1 which expose the outer peripheral portion ofthe surface 41A of the metal layer 41, by a single etching process,because the metal layer 91 and the metal layer 42 are made of the samemetal material. Hence, it is possible to reduce the fabrication cost ofthe wiring board 86.

Next, in an insulator layer forming process illustrated in FIG. 45, theinsulator layer 21 is formed to cover the projecting parts 91-1, theelectrode pads 88, and the surface 55A of the support plate 55 on theside formed with the projecting parts 91-1. In addition, the openings 38are formed in the insulator layer 21 at portions opposing the surface75A of the metal layer 75, to expose the surface 75A of the metal layer75.

Accordingly, the insulator layer 21 covers the outer peripheral portionof the surface (surface 41A of the metal layer 41) of the electrode pads88 on the side provided with the terminals 12. Consequently, it ispossible to suppress the generation of delamination between the sidesurface of the electrode pad 88 and the side surface of the insulatorlayer 21, and the reliability of the wiring board 86 can be improved.

In addition, the width of the outer peripheral portion of the surface41A of the metal layer 41 covered by the insulator layer 21 may be 0.1μm to 6 μm, and preferably 1 μm to 3 μm, for example.

Next, in a process illustrated in FIG. 46, a process similar to theprocess of the second embodiment described above in conjunction withFIG. 23, including the conductor pattern forming process, is carried outto form the conductor patterns 27 and 28, the vias 31, the pads 32, andthe solder resist layer 34. Hence, a structure corresponding to thewiring board 86 is formed on the support plate 55.

Next, in a support plate removing process illustrated in FIG. 47, thesupport plate 55 in FIG. 46 is removed by a process similar to theprocess of the second embodiment described above in conjunction withFIG. 24.

Next, in a projecting part removing process illustrated in FIG. 48, theprojecting parts 91-1 in FIG. 47 are removed by using an etchant whichremoves only the projecting parts 91-1.

Next, in a process illustrated in FIG. 49, a process similar to theprocess of the second embodiment described above in conjunction withFIG. 25 is carried out to fabricate the semiconductor device 85 of thisthird embodiment.

According to the method of fabricating the wiring board 86 of this thirdembodiment, it is possible to simultaneously form the recesses 89 andthe projecting parts 91-1 which expose the outer peripheral portion ofthe surface 41A of the metal layer 41, by a single etching process,because the metal layer 91 and the metal layer 42 are made of the samemetal material. Hence, it is possible to reduce the fabrication cost ofthe wiring board 86.

Furthermore, after exposing the outer peripheral portion of the surface41A of the metal layer 41 and forming the recesses 89 in the electrodepads 88, the insulator layer 21 is formed to cover the projecting parts91-1, the electrode pads 88, and the surface 55A of the support plate 55on the side formed with the projecting parts 91-1, in order to fill therecesses 89 by the insulator layer 21. As a result, the bonding betweenthe electrode pads 88 and the insulator layer 21 is improved, and thepositions of the electrode pads 88 are restricted within the insulatorlayer 21.

Fourth Embodiment

FIG. 50 is a cross sectional view illustrating the semiconductor devicein a fourth embodiment of the present invention. In FIG. 50, those partsthat are the same as those corresponding parts of the semiconductordevice 10 of the first embodiment illustrated in FIG. 2 are designatedby the same reference numerals.

As illustrated in FIG. 50, a semiconductor device 95 in this fourthembodiment is provided with a wiring board 96, in place of the wiringboard 11 provided in the semiconductor device 10 of the firstembodiment. Otherwise, the structure of the semiconductor device 95 isbasically the same as that of the semiconductor device 10.

The wiring board 96 is provided with electrode pads 98 formed by asingle metal layer, in place of the electrode pads 25 provided in thewiring board 11. Otherwise, the structure of the wiring board 96 isbasically the same as that of the wiring board 11.

The electrode pads 98 are embedded within the insulator layer 21. Aportion of a surface 98A of the electrode pad 98 is exposed at theopening 38. The portion of the electrode pad 98 exposed by the opening38 is connected to the conductor pattern 27.

A central portion of a surface 98B of the electrode pad 98 on the sideformed with the terminal 12, is exposed at the opening 37. An outerperipheral portion of the surface 985 of the electrode pad 98 is coveredby the insulator layer 21.

By covering the outer peripheral portion of the surface 98B of theelectrode pad 98 on the side formed with the terminal 12, by theinsulator layer 21, it is possible to suppress the generation ofdelamination between the side surface of the electrode pad 98 and theside surface of the insulator layer 21. Hence, the reliability of thewiring board 96 can be improved.

The portion of the electrode pad 98 exposed at the opening 37 iselectrically connected to the electronic component 13 via the terminal12.

For example, Cu may be used for the electrode pads 98. In this case, thethickness of the electrode pad 98 may be 10 μm to 20 μm, and preferably15 μm, for example.

When Cu is used for the electrode pads 98 and the metal material formingthe conductor pattern 27 is also Cu, it is possible to improve thebonding between the electrode pads 98 and the conductor pattern 27. As aresult, it is possible to improve the reliability of the electricalconnection between the electrode pads 98 and the conductor pattern 27.

In a case where the electrode pads 98 are used to mount the electroniccomponent 13 on the wiring board 96, the diameter of the electrode pad98 may be 50 μm to 150 μm, for example. In addition, when the pads 32are used to mount the electronic component 13 on the wiring board 96 andthe electrode pads 98 are used to connect the wiring board 96 to acircuit board (not shown), the diameter of the electrode pad 98 may be200 μm to 1000 μm, for example.

According to the semiconductor device 95 of this fourth embodiment, theouter peripheral portion of the surface 98B of the electrode pad 98 onthe side formed with the terminal 12 is covered by the insulator layer21. For this reason, it is possible to suppress the generation ofdelamination between the side surface of the electrode pad 98 and theside surface of the insulator layer 21, and the reliability of thewiring board 96 can be improved.

In addition, when Cu is used for the electrode pads 98 and the metalmaterial forming the conductor pattern 27 is also Cu, it is possible toimprove the bonding between the electrode pads 98 and the conductorpattern 27. As a result, it is possible to improve the reliability ofthe electrical connection between the electrode pads 98 and theconductor pattern 27.

Furthermore, it is possible to reduce the cost of the wiring board 96 byforming the electrode pads 98 by a single metal layer.

FIGS. 51 through 59 are cross sectional views for explaining fabricationprocesses of the semiconductor device in the fourth embodiment of thepresent invention. In FIGS. 51 through 59, those parts that are the sameas those corresponding parts of the semiconductor device 95 of thefourth embodiment illustrated in FIG. 50 are designated by the samereference numerals.

A description will be given of the method of fabricating thesemiconductor device 95 of this fourth embodiment, by referring to FIGS.51 through 59. First, a process similar to the process of the firstembodiment described above in conjunction with FIG. 3 is carried out toform the structure illustrated in FIG. 3.

Next, in a metal layer forming process for the projecting partillustrated in FIG. 51, a metal layer 101 for forming the projectingpart, made of a material different from the first metal, is formed onthe surface 55A of the support plate 55 at portions exposed by theopenings 56A. More particularly, the metal layer 101 is formed byelectroplating using the support plate 55 as a feed layer, for example.For example, the metal layer 101 may be formed by a Ni layer, a Snlayer, a Sn—Pb layer or the like. In this case, the thickness of themetal layer 101 may be 1 μm to 30 μm, and preferably 20 μm, for example.

Next, in an electrode pad forming process illustrated in FIG. 52, theelectrode pads 98 made of the first metal (for example, Cu) are formedon a surface 101A of the metal layer 101. More particularly, a Cu layeris formed by electroplating using the support plate 55 as a feed layer,for example, in order to form the electrode pads 98.

Next, in a process illustrated in FIG. 53, the resist layer 56 isremoved. Next, in a projecting part forming process illustrated in FIG.54, the metal layer 101 is etched using an etchant which etches only themetal layer 101, to form projecting parts 101-1 which exposes the outerperipheral portion of the surface 98B of the electrode pads 98 on theside making contact with the metal layer 101.

By carrying out an isotropic wet etching using the electrode pads 98 asa mask, it is possible to expose the outer peripheral portion of thesurface 98B of the metal layer 98 from the projecting parts 101-1,utilizing the side etching and undercut with respect to the metal layer101 achieved by the etchant.

For example, the projecting part 101-1 may have a truncated cone shape.In this case, in the cross sectional view, the side surface of theprojecting part 101-1 having the truncated cone shape may be curvedinwards in a gull-wing shape relative to a center axis of the truncatedcone shape.

Next, in an insulator layer forming process illustrated in FIG. 55, theinsulator layer 21 having the openings 38 is formed after the projectingpart forming process to cover the projecting parts 101-1, the electrodepads 98, and the surface 55A of the support plate 55 on the side formedwith the projecting parts 101-1.

By forming the insulator layer 21 to cover the outer peripheral portionof the surface 98B of the electrode pads 98 on the side formed with theterminals 12, it is possible to suppress the generation of delaminationbetween the side surface of the electrode pad 98 and the side surface ofthe insulator layer 21. As a result, the reliability of the wiring board96 can be improved.

The width of the outer peripheral portion of the surface 985 of theelectrode pad 98 at the portion covered by the insulator layer 21 may be0.1 μm to 6 μm, and preferably 1 μm to 3 μm, for example.

Next, in a process illustrated in FIG. 56, a process similar to theprocess of the third embodiment described above in conjunction with FIG.46 is carried out to form the conductor patterns 27 and 28, the vias 31,the pads 32, and the solder resist layer 34. As a result, a structurecorresponding to the wiring board 96 is formed on the support plate 55.

Next, in a support plate removing process illustrated in FIG. 57, thesupport plate 55 is removed by a process similar to the process of thethird embodiment described above in conjunction with FIG. 47.

Next, in a projecting part removing process illustrated in FIG. 58, theprojecting parts 101-1 are removed using an etchant which etches onlythe projecting parts 101-1. Hence, a portion of the surface 98B of theelectrode pads 98 on the side contacting the projecting parts 101-1 isexposed, to thereby form the openings 37 having shapes corresponding tothe shapes of the etched projecting parts 101-1. As a result, the wiringboard 96 of the fourth embodiment is fabricated.

According to the method of fabricating the wiring board 96 of thisfourth embodiment, the insulator layer 21 is formed to cover the outerperipheral portion of the surface 98B of the electrode pads 98 on theside formed with the terminals 12. For this reason, it is possible tosuppress the delamination between the side surface of the electrode pad98 and the side surface of the insulator layer 21, and the reliabilityof the wiring board 96 can be improved.

In addition, by forming the electrode pads 98 in the electrode padforming process by forming only a single metal layer, the fabricationcost of the wiring board 96 can be reduced.

FIG. 60 is a cross sectional view illustrating an example of anotherwiring board. In FIG. 60, those parts that are the same as the wiringboard 96 of the fourth embodiment illustrated in FIG. 50 are designatedby the same reference numerals.

It is possible to use a wiring board 110 illustrated in FIG. 60 in placeof the wiring board 96 provided in the semiconductor device 95 of thefourth embodiment.

As illustrated in FIG. 60, the wiring board 110 has an OrganicSolderbility Preservative (OSP) layer 111 provided on the surface 98B ofthe electrode pads 98. Otherwise, the structure of the wiring board 110is basically the same as the structure of the wiring board 96.

When the wiring board 110 having the structure described above is usedin the semiconductor device 95, it is possible to secure sufficientwetting between the electrode pads 98 and solder when the solder is usedfor the terminal 12. Further, it is possible to prevent oxidation of thesurface 98B of the electrode pads 98.

The surface 98B of the electrode pads 98 are processed by the OSP toform the OSP layer 111 on the surface 98B of the electrode pads 98 atthe portions exposed by the openings 37 in an OSP layer forming processthat is carried out between the projecting part removing processillustrated in FIG. 58 and the process illustrated in FIG. 59.Otherwise, the wiring board 110 may be fabricated by processes similarto the processes used to fabricate the wiring board 96 of the fourthembodiment.

FIG. 61 is a cross sectional view illustrating the semiconductor devicein a modification of the second embodiment of the present invention. Ina semiconductor device 120 of this modification of the secondembodiment, the electronic component 13 is connected to the pads 32.Otherwise, the structure of the semiconductor device 120 is basicallythe same as the structure of the semiconductor device 70 of the secondembodiment. According to the semiconductor device 120, it is possible toobtain effects similar to the effects obtainable in the semiconductordevice 70.

FIG. 62 is a cross sectional view illustrating the semiconductor devicein a modification of the third embodiment of the present invention. In asemiconductor device 130 of this modification of the third embodiment,the electronic component 13 is connected to the pads 32. Otherwise, thestructure of the semiconductor device 130 is basically the same as thestructure of the semiconductor device 85 of the third embodiment.According to the semiconductor device 130, it is possible to obtaineffects similar to the effects obtainable in the semiconductor device85.

FIG. 63 is a cross sectional view illustrating the semiconductor devicein a modification of the fourth embodiment of the present invention. Ina semiconductor device 140 of this modification of the fourthembodiment, the electronic component 13 is connected to the pads 32.Otherwise, the structure of the semiconductor device 140 is basicallythe same as the structure of the semiconductor device 95 of the fourthembodiment. According to the semiconductor device 140, it is possible toobtain effects similar to the effects obtainable in the semiconductordevice 95.

In each of the embodiments and modifications of the present invention,the metal layer for forming the projecting part may have an electricalconductivity different from that of the first metal.

Moreover, in each of the embodiments and modifications of the presentinvention, an underfill resin may be provided between the electroniccomponent and the wiring board.

The embodiments and modifications of the present invention areapplicable to wiring boards having electrode pads, conductor patternsconnected to the electrode pads and an insulator layer embedded with theelectrodes and the conductor patterns, and to methods of fabricatingsuch wiring boards.

Further, the present invention is not limited to these embodiments, butvarious variations and modifications may be made without departing fromthe scope of the present invention.

1. A wiring board comprising: an electrode pad having a first surfaceand a second surface located on an opposite side from the first surface;a conductor pattern connected to the first surface of the electrode pad;and an insulator layer embedded with the electrode pad and the conductorpattern, wherein the insulator layer covers an outer peripheral portionof the second surface of the electrode pad.
 2. The wiring board asclaimed in claim 1, wherein: the insulator layer has an opening exposinga portion of the second surface; and the opening has a shape that widensfrom the electrode pad in towards a direction away from the electrodepad.
 3. The wiring board as claimed in claim 1, wherein: the electrodepad includes a first metal layer exposed at the opening and made of ametal different from a metal forming the conductor pattern, a secondmetal layer provided on the first metal layer and made of a metaldifferent from the metal forming the conductor pattern, and a thirdmetal layer provided on the second metal layer and made of the metalforming the conductor pattern; and the third metal layer connects to theconductor pattern.
 4. The wiring board as claimed in claim 3, whereinouter peripheral side surfaces of the second metal layer are disposed onan inner side compared to outer peripheral side surfaces of each of thefirst metal layer and the third metal layer.
 5. The wiring board asclaimed in claim 1, wherein the electrode pad is made of a metal formingthe conductor pattern, and further comprising: an Organic SolderbilityPreservative (OSP) layer covering the second surface of the electrodepad at a portion exposed at the opening.
 6. A method of fabricating awiring board, comprising: an electrode pad forming step forming anelectrode pad on a support plate made of a first metal; a projectingpart forming step forming, on the support plate at a portion opposingthe electrode pad, a projecting part which exposes a surface of theelectrode pad on a side opposing the support plate and contacts theelectrode pad, by etching the support plate; an insulator layer formingstep forming an insulator layer covering the electrode pad, theprojecting part, and a surface of the support plate formed with theprojecting part; a conductor pattern forming step forming, on theinsulator layer, a conductor pattern connected to the electrode pad; anda support plate removing step removing the support plate formed with theprojecting part by an etching, after the conductor pattern forming step,to thereby expose a portion of the surface of the electrode pad on theside opposing the support plate and form in the insulator layer anopening having a shape corresponding to a shape of the projecting part.7. The method of fabricating the wiring board as claimed in claim 6,wherein the projecting part forming step etches the support plate sothat the shape of the projecting part widens from the electrode padtowards the support plate.
 8. The method of fabricating the wiring boardas claimed in claim 6, wherein: the electrode pad forming step includes:a first metal layer forming step forming a first metal layer made of ametal different from the first metal; and a second metal layer formingstep forming, on the first metal layer, a second metal layer made of ametal different from the first metal, wherein the projecting partforming step etches the support plate using the electrode pad as a maskand using an etchant which selectively etches the first metal.
 9. Themethod of fabricating the wiring board as claimed in claim 8, wherein:the electrode pad forming step further includes: a third metal layerforming step forming, on a surface of the second metal layer, a thirdmetal layer made of the first metal, after the second metal layerforming step, wherein the third metal layer forming step forms the thirdmetal layer to a thickness sufficient to cover the surface of the secondmetal layer after the projecting part forming step is carried out. 10.The method of fabricating the wiring board as claimed in claim 8,wherein: the electrode pad forming step further includes: a third metallayer forming step forming, on a surface of the second metal layer, athird metal layer made of the first metal, after the second metal layerforming step; and a protection layer forming step forming, on the thirdmetal layer, a protection layer which prevents etching of the thirdmetal layer when the support plate is etched in the projecting partforming step, and further comprising: a protection layer removing stepremoving the protection layer, between the projecting part forming stepand the insulator layer forming step.
 11. The method of fabricating thewiring board as claimed in claim 6, further comprising: a heightadjusting layer forming step forming a height adjusting layer made ofthe first metal on a portion of the support plate corresponding to aregion where the electrode pad is formed, prior to the electrode padforming step, wherein the support plate removing step removes the heightadjusting layer together with the support plate using the etchant whichselectively etches the first metal.
 12. A method of fabricating a wiringboard, comprising: a metal layer forming step forming a metal layer on asupport plate made of a first metal; an electrode pad forming stepforming an electrode pad on the metal layer; a projecting part formingstep forming a projecting part by etching the metal layer, and exposingan outer peripheral portion of a surface of the electrode pad in contactwith the projecting part; an insulator layer forming step forming aninsulator layer to cover the projecting part, the electrode pad, and asurface of the support plate formed with the projecting part, after theprojecting part forming step; a conductor pattern forming step forming,on the insulator layer, a conductor pattern connected to the electrodepad; a support plate removing step removing the support plate by anetching, after the conductor pattern forming step; and a projecting partremoving step removing the projecting part, after the conductor patternforming step, to thereby expose a portion of the surface of theelectrode pad in contact with the projecting part and form in theinsulator layer an opening having a shape corresponding to a shape ofthe projecting part.
 13. The method of fabricating the wiring board asclaimed in claim 12, wherein the metal layer is made of a materialhaving an electrical conductivity different from that of the firstmetal.
 14. The method of fabricating the wiring board as claimed inclaim 12, wherein the electrode pad is made of the first metal.
 15. Themethod of fabricating the wiring board as claimed in claim 12, whereinthe electrode pad forming step includes successively stacking, on themetal layer, a first metal layer made of a metal different from thefirst metal, a second metal layer made of a metal different from thefirst metal, and a third metal layer made of the first metal, to therebyform the electrode pad.
 16. The method of fabricating the wiring boardas claimed in claim 15, wherein the electrode pad forming step forms thesecond metal layer using a metal forming the metal layer.
 17. The methodof fabricating the wiring board as claimed in claim 12, furthercomprising: a step forming an Organic Solderbility Preservative (OSP)layer on a portion of the electrode pad exposed from the insulator layerby carrying out an Organic Solderbility Preservative (OSP) process.